1. Field of the Invention
Generally, the present disclosure relates to sophisticated integrated circuits including advanced transistor elements that comprise highly capacitive gate structures including a metal-containing electrode and a high-k gate dielectric.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a large number of circuit elements to be formed on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith, the reduction of channel resistivity and reduction of gate resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are fabricated on the basis of silicon due to the substantially unlimited availability thereof, the well-understood characteristics of silicon and related materials and processes and the experience gathered over the last 50 years. Therefore, silicon will likely remain the material of choice in the foreseeable future for circuit generations designed for mass products. One reason for the importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or other metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current due to the required enhanced capacitive coupling of the gate electrode to the channel region that is accomplished by decreasing the thickness of the silicon dioxide layer. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although generally usage of high speed transistor elements having an extremely short channel may be restricted to high-speed signal paths, whereas transistor elements with a longer channel may be used for less critical signal paths, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may no longer be compatible with requirements for many types of integrated circuits.
Therefore, replacing silicon dioxide, or at least a part thereof, as the material for gate insulation layers has been considered. Possible alternative dielectrics include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer nevertheless provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. It has thus been suggested to replace silicon dioxide with high permittivity materials such as tantalum oxide (Ta2O5), with a k of approximately 25, strontium titanium oxide (SrTiO3), having a k of approximately 150, hafnium oxide (HfO2), HfSiO, zirconium oxide (ZrO2) and the like.
When advancing to sophisticated gate architecture based on high-k dielectrics, additionally, transistor performance may also be increased by providing an appropriate conductive material for the gate electrode so as to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides enhanced capacitance, even at a less critical thickness compared to a silicon dioxide layer, while additionally maintaining leakage currents at an acceptable level. On the other hand, metal-containing non-polysilicon material, such as titanium nitride and the like, may be formed so as to directly connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone. Therefore, the threshold voltage of the transistors is significantly affected by the work function of the gate material that is in contact with the gate dielectric material, and an appropriate adjustment of the effective work function with respect to the conductivity type of the transistor under consideration has to be guaranteed.
For example, appropriate metal-containing gate electrode materials, such as titanium nitride and the like, may frequently be used in combination with appropriate metal species, such as lanthanum, aluminum and the like, so as to adjust the work function to be appropriate for each type of transistor, i.e., N-channel transistors and P-channel transistors, which may require an additional band gap offset for the P-channel transistor. For this reason, it has also been proposed to appropriately adjust the threshold voltage of transistor devices by providing a specifically designed semiconductor material at the interface between the high-k dielectric material and the channel region of the transistor device, in order to appropriately “adapt” the band gap of the specifically designed semiconductor material to the work function of the metal-containing gate electrode material, thereby obtaining the desired low threshold voltage of the transistor under consideration. Typically, a corresponding specifically designed semiconductor material, such as silicon/germanium and the like, may be provided by an epitaxial growth technique at an early manufacturing stage, which may also present an additional complex process step, which, however, may avoid complex processes in an advanced stage for adjusting the work function and thus the threshold voltages in a very advanced process stage.
Basically, the concept of forming sophisticated gate electrode structures in an early manufacturing stage on the basis of a threshold voltage adjusting semiconductor alloy is a very promising process sequence since very complex process steps for replacing conventional gate materials in a very advanced manufacturing stage, as is typically associated with so-called replacement gate approaches, may require significant modifications of the overall process flow at a final phase of providing the semiconductor-based circuit elements. Consequently, many process strategies have been proposed in which a silicon/germanium alloy may be selectively formed as a part of one type of active region, while other active regions, such as active regions for N-channel transistors or any other transistors, which do not require the incorporation of a threshold voltage adjusting material, may be appropriately masked. To this end, any appropriate hard mask material may be provided and patterned so as to expose the active regions under consideration, which are then exposed to a deposition atmosphere in order to form the desired threshold voltage adjusting semiconductor material on the basis of selective epitaxial growth techniques. During this deposition process, the material composition and the layer thickness have to be precisely controlled in order to reduce the overall variability of transistor characteristics, such as the threshold voltage. For example, in a silicon/germanium alloy, a germanium concentration of up to 25 atomic percent and a layer thickness of approximately 8-50 nm may be selected in order to obtain the required threshold voltages of sophisticated P-channel transistors having a gate length of 50 nm and less. It turns out, however, that even minute variations of any of these parameters may strongly influence the finally obtained transistor characteristics, wherein, in particular, a significant variance of the threshold voltage may be observed with respect to a difference in transistor width or otherwise the same transistor devices. Since it is believed that, in particular, any edge effects upon selectively growing the semiconductor alloy in the active region may have a pronounced influence on the finally obtained material characteristics, it has been proposed to provide superior deposition characteristics by recessing the active region prior to actually growing the semiconductor alloy. In this manner, highly uniform growth conditions may be obtained across the entire active region since the dielectric material of the isolation regions that laterally delineate the active region suppress any lateral growth and thus also provide well-defined growth conditions at the edges of the active regions. To this end, highly efficient etch strategies have been developed in which, in some very promising approaches, the corresponding etch process is performed in situ with the actual selective growth process, i.e., an appropriate etch atmosphere is established within the deposition reactor, wherein the material of the active region is removed in a highly selective manner with respect to the trench isolation region. For example, an etch atmosphere on the basis of hydrochloric acid (HCl) may be readily established in the deposition chamber by using similar precursor gases, for instance except for a reducing gas component, so that a very efficient etch process may be established in order to form a recess having a desired depth, thereby achieving the superior deposition conditions. At the same time, the recessing may be controlled in order to achieve a highly planar surface topography with respect to other active regions, which are masked during the selective deposition process. In this manner, the subsequent patterning process for forming the sophisticated gate electrode structures may be performed on similar height levels for any active region.
Although the above-described process sequence is basically a very efficient mechanism for implementing the threshold voltage adjusting semiconductor alloy, it turns out that significant device failures may be observed, as will be described in more detail with reference to FIGS. 1a and 1b. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in an early manufacturing stage. As shown, the device 100 comprises a substrate 101 such as a silicon substrate or any other appropriate carrier material which has formed thereon a semiconductor layer 102, typically a silicon-based semiconductor material. Furthermore, in some cases, a silicon-on-insulator (SOI) configuration is provided for the device 100, in which case a buried insulating material (not shown) is formed directly below the semiconductor layer 102. In other cases, a bulk configuration is formed by the layer 102 and the substrate 101, in which case the semiconductor material 102 is initially a portion of or directly connects to a crystalline semiconductor material of the substrate 101. Furthermore, in the manufacturing stage shown, a plurality of active regions, which are to be understood as semiconductor regions in and above which one or more transistor elements are to be formed, laterally delineated by a trench isolation structure 102C. For convenience, active regions 102A, 102B are illustrated, wherein the active regions 102A receive a semiconductor alloy 103A, while the active region 102B is masked by an appropriate hard mask material 104.
The semiconductor device 100 is formed on the basis of the following process techniques. The trench isolation region 102C is typically formed by applying sophisticated lithography techniques in which appropriate hard mask materials are patterned so as to define the position, lateral size and shape of active regions 102A, 102B. Thereafter, sophisticated etch techniques are applied in order to form trenches in the semiconductor layer 102, which are subsequently filled with a dielectric material such as silicon dioxide. To this end, high density plasma deposition techniques have proven to be viable process techniques for reliably filling the trenches without creating any voids. Frequently, the high density plasma deposition process is actually a sequence of deposition and etch processes wherein a previously formed sub-layer may be re-etched, for instance on the basis of a nitrogen fluoride-containing reactive process atmosphere, in order to preferably remove material on the edges of the corresponding trenches. Thereafter, a further deposition process may be applied, followed by another etch process, thereby increasingly filling the trenches from bottom to top substantially without creating any voids in the trench isolation region 102C. Thereafter, anneal processes may be applied and excess material may be removed by planarization techniques. Prior to or after forming the trench isolation region 102C, a basic dopant profile may be established in the active regions 102A, 102B in accordance with the overall transistor requirements. To this end, well-established implantation techniques and masking regimes are available. Thereafter, a hard mask material such as silicon dioxide, silicon nitride and the like may be formed, for instance, by oxidation, deposition and the like, and the resulting layer is patterned by using lithography techniques in order to mask any active regions that do not require a threshold voltage adaptation on the basis of an additional semiconductor material. For example, the active region 102B is illustrated as a corresponding region which may, for instance, receive an N-channel transistor during the further processing. Thereafter, any cleaning processes may be applied, for instance, on the basis of hydrofluoric acid (HF) so as to remove contaminants, native oxides and the like. Next, the device 100 is brought into a process environment 130, for instance in the form of a deposition process chamber in which initially a reactive etch atmosphere is established, as indicated by 131, in order to recess any exposed active regions, such as the regions 102A, which may be accomplished on the basis of hydrochloric acid (HCl), as discussed above. In this manner, recesses 102R may be formed in a highly controllable manner without unduly contaminating any exposed surface areas of the device 100. As discussed above, the degree of recessing 102R may be adjusted so as to obtain, after the deposition of the semiconductor alloy 103A on the basis of a selective deposition process 132, a desired overall surface topography. It is well known that a selective epitaxial growth process may be performed on the basis of appropriate precursor materials and process parameters so as to initiate the growth of semiconductor material 103A on exposed crystalline surface areas, such as (100) crystal planes of the active regions 102A, while a pronounced material deposition on any dielectric surface areas is significantly suppressed. Consequently, the recesses 102R may provide substantially uniform growth conditions across the entire active regions 102A and also at the edges of the trench isolation region 102C.
FIG. 1b schematically illustrates the device 100 after completing the above-described process sequence within the process environment 130 (FIG. 1a), wherein frequently very pronounced irregularities may be observed. For example, in one of the active regions 102A, a significant portion of the base material may have been removed during the preceding process sequence and thus material 103A may be formed only in a non-controllable manner or a corresponding active region 102A may comprise substantially no semiconductor material at all. Irrespective of the amount of any remaining semiconductor material, as indicated by 102D, the further processing for the respective active region 102A may, therefore, result in a severe device failure, such as a missing transistor of a memory cell and the like.
Thus, although basically a very efficient overall process flow may be provided on the basis of the sequence as described above in which, in principle, highly uniform deposition conditions may be provided, the application of the above-described process sequence in a production environment is less than desirable due to the above-described significant irregularities after formation of the threshold voltage adjusting semiconductor alloy 103A.
In view of the situation described above, the present disclosure relates to manufacturing techniques and semiconductor devices in which a semiconductor alloy may be formed selectively on active regions on the basis of a recessed surface configuration formed on the basis of an in situ process, while avoiding or at least reducing the effects of one or more of the problems identified above.